1. Field of the Invention
The present invention relates to a receiver including a data processing unit adapted so as to correct two-bit errors in received data by using a cyclic redundancy check (CRC) code.
The present invention relates to a receiver including a data processing unit for determining errors in data to be checked by using the cyclic redundancy check (CRC) code.
The present invention also relates to a receiver including an ID controlling portable synchronous serial data receiving apparatus having a timer function.
The present invention further relates to a receiver including an ID controlling portable serial data receiving apparatus used for a radio paging apparatus (hereinafter referred to as a pager) or the like.
2. Description of the Related Art
As a circuit for correcting errors within received data encoded by a CRC code, a circuit shown in FIG. 10 is known for example. An error correction circuit 100 shown in FIG. 10 comprises a shift register circuit 105 for holding data to be checked SIG having a certain number of bits in response to a clock signal CLK2, a syndrome generating circuit 103 for generating syndromes by implementing a modulo-two arithmetic on the data to be checked SIG in response to a clock signal CLK1 and a decoder ROM 300 for decoding syndrome data generated by the syndrome generating circuit 103.
The decoder ROM 300 is arranged so as to instruct to make a correction on an error bit indicated by the syndrome data. The error in the received data is corrected by turning a selection signal SELECT to a xe2x80x9cHxe2x80x9d level with a predetermined timing and supplying one pulse as the clock signal CLK2 to the shift register circuit 105. The resultant data is held within the shift register circuit 105 by being shifted by one bit.
A data processing circuit for detecting a boundary of words utilizing error detection by means of BCH code is known to be used in a paging decoder for example to synchronize bit serial input data transmitted per bit in a time-division manner with the internal operation. The prior art data processing circuit of this type is arranged so as to detect errors in input data having a predetermined number of bits N by means of the BCH code by N times, to acquire next one bit anew when it is determined that there exists an error and to repeat the same process for detecting errors again by N times until it is determined that there exists no more error.
FIGS. 19 through 24 show one example of the prior art data processing circuit of this type. The data processing circuit 101 shown in FIGS. 19 through 24 comprises a data register 102, a syndrome generating circuit 103 and a switching circuit 224 for selectively supplying either input data RD from an input terminal 223 or an output of the data register 102 to an input terminal 223 of the data register 102 in response to a selection control signal SL.
The data register 102 is a shift register circuit having a known structure for holding data supplied to its input terminal by acquiring it on a bit-by-bit basis in response to a clock pulse CL supplied from a clock input terminal 225 every time when the clock pulse CL is input. The held data may be taken out of its output terminal 246 in response to the clock pulse CL.
The syndrome generating circuit 103 is a circuit for generating a syndrome by acquiring the input data RD in response to a the clock pulse CL supplied via an AND gate 252 when the selection control signal turns to xe2x80x9cHxe2x80x9d level and by implementing modulo-two arithmetic. A logical circuit 106 determines whether a value of the generated syndrome is 0 or not.
The result determined by the logical circuit 106 is supplied as a set signal to a flip-flop 243 which has been put into a reset state by a first set signal RT1 from a terminal 250 when a check pulse CH is added from a terminal 251.
The data processing circuit 101 operates as follows. This will be explained with reference to FIG. 25. At first, when the first reset signal RT1 and a second reset signal RT2 supplied to a terminal 226 turn to xe2x80x9cLxe2x80x9d level for a short time at time T1, the data register 102, the syndrome generating circuit 103 and the flip-flop 243 are reset, respectively, thereby completing their initialization. After that, 31 clock pulses CL are output when the selection control signal SL is at the xe2x80x9cLxe2x80x9d level and thereby 31 bits of input data RD is taken into the data register 102.
Next, when the selection control signal SL is switched from a xe2x80x9cLxe2x80x9d level to xe2x80x9cHxe2x80x9d level at time T2, a loop structure in which an output of the data register 102 is returned to its input is formed and the 31 bits of data held in the data register 102 is cyclically shifted per bit by 31 clock pulses CL supplied after time T2.
At the same time, those 31 clock pulses CL are supplied also to the syndrome generating circuit 103 via an AND gate 252 opened by the selection control signal SL and thereby the syndrome for the 31 bits of data held in the data register 102 is calculated.
A value of the syndrome is stored in the flip-flop 243 by the check pulse CH output at time T3. If the value of the syndrome at this time is 0, a level of the detection terminal 245 turns to xe2x80x9cHxe2x80x9d, meaning that the word boundary could have been detected. However, if the value of the syndrome is a number other than 0, data of the next bit is taken in to be checked.
That is, after turning the level of the selection control signal to xe2x80x9cLxe2x80x9d at time T4, only one clock pulse CL is given at time T5 to input one new bit data to the data register 102 and the syndrome generating circuit 103 is reset by the first reset signal RT1 at time T6.
Then, the level of the selection control signal SL is turned from xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d at time T7 to supply 31 clock pulses CL again to execute the calculation of a syndrome for the new set of input data held in the data register 102.
Thus, the acquisition of one bit of data and the calculation of a syndrome are repeatedly executed until the value of the syndrome becomes 0, i.e. until the word boundary is detected.
As a synchronous serial data receiving apparatus, one as shown in FIG. 27 in block diagram form has been used in the past. This receiving apparatus has bit synchronizing means and word synchronizing means and determines whether data should be received or not by determining whether it is in a state synchronous or asynchronous to a signal to be transmitted.
FIG. 29 shows a transition of receiving state of the prior art serial data receiving apparatus. This is considered to correspond only to RUN mode in FIG. 28 and only the receiving state shifts between an asynchronous state and a synchronous state in response to detection and non-detection of a synchronous code.
In FIG. 27, a timer counter 112 and a timing generating circuit 113 connected to an oscillation circuit 111 supply a timer function and operation timing clocks of each part, respectively. At first, the bit synchronizing means 118 establishes a bit synchronism with an input signal input from a data input terminal 117. Next, the word synchronizing means 119 establishes a word synchronism. When the word synchronism has been established, the word synchronizing means 119 outputs a control signal to the timing generating means 113 and starts to receive ID and data. The received ID is compared with a content in ID storage means 122 by ID collating means 121. When the ID is collated without any trouble, a control signal is output from the ID collating means 121 to the timing generating means 113 to continue to receive the data. When the ID cannot be collated, the receiving is terminated. The received data is once stored in data storage means 120 and is output from a data output terminal 124 via an output circuit 123.
The ID storage means 122 is normally composed of a register. The content therein is written generally from a control input terminal 116 during the initialization. There is a possibility that an erroneous operation is ensued during the collation of IDs if the ID is rewritten during receiving. Therefore, it is necessary to initialize to stop the receiving once in resetting the ID.
As an ID controlling portable serial data receiving apparatus used for a pager or the like, one as shown in FIG. 31 in block diagram form has been used in the past. In the figure, a line with a short slant line indicates that it comprises a plurality of lines. The receiving apparatus comprises a decoder circuit A having a synchronizing circuit 132, an error correction circuit 133, an ID collating or comparison circuit 134 and a control circuit 135, a microprocessor circuit B having a CPU core circuit 136, a data RAM 138 and a program ROM 137 and a register circuit 139 for bridging data from the decoder circuit A.
In FIG. 31, a serial data input 131 is input to the synchronizing circuit 132 within the decoder circuit A. When synchronism is established by the synchronizing circuit 132, the data is acquired in succession. The acquired data is corrected as necessary by the error correction circuit 133 and it is determined if the ID coincides or not by the ID collating circuit 134. When it is confirmed that the ID coincides, a message is received in succession. Errors in the received message are corrected similarly to the case of the ID. Then, information on the received ID, the message and accompanying error information are stored in the register circuit 139. When the ID is confirmed to coincide and the ID information and message are stored in the register circuit 139, the control circuit 135 in the decoder circuit A generates an interrupt request by way of an interrupt control signal 142 to the CPU core circuit 136 of the microprocessor circuit B. In response to the interrupt request, the microprocessor circuit B accesses the register circuit 139. Thus, the received address information and message information are taken into the microprocessor circuit B.
It is also possible to use another conventional method for the interface between the decoder circuit A and the microprocessor circuit B. A micro-controller carrying a DMAC is described in Japanese Patent Publication No. 59-42331. The use of DMA eliminates the necessity to operate the CPU core circuit 136 fully in writing the data received by the decoder circuit A to the data RAM 138. The operation in this case is carried out as follows.
Because the operation until the time the interrupt is generated after receiving the serial data input is the same with that described above, its explanation is omitted here. In response to the interrupt request, the microprocessor B executes a DMA instruction. When the DMA instruction is executed, the data received by the decoder circuit A is transferred to and stored in the data RAM 138 in synchronism with system clock timing of the CPU core circuit 136. When all the received data is written to the data RAM 138, the microprocessor circuit ends the DMA operation.
As another ID control portable serial data receiving apparatus used for a pager or the like, one as shown in FIG. 34 in block diagram form has been used in the past. The receiving apparatus comprises a decoder circuit A having a synchronizing circuit 132, an error correction circuit 133, an ID collating circuit 134 and a control circuit 135, a microprocessor circuit B having a CPU core circuit 136, a data RAM 138 and a program ROM 137 and a register circuit 139 for bridging data from the decoder circuit A.
In FIG. 34, a serial data input 131 is input to the synchronizing circuit 132 within the decoder circuit A. When a synchronism is established by the synchronizing circuit 132, the data is acquired in succession. The acquired data is corrected as necessary by the error correction circuit 133 and is determined if its ID coincides or not by the ID collating circuit 134. When it is confirmed that the ID coincides, a message is received in succession. Errors in the received message are corrected similarly to the case of the ID. Then, the information of received ID, message and accompanying error information are stored in the register circuit 139. When the ID is confirmed to coincide and the ID information and message are stored in the register circuit 139, the control circuit 135 in the decoder circuit A generates an interrupt request by way of an interrupt control signal 132 to the CPU core circuit 136 of the microprocessor circuit B. In response to the interrupt request, the microprocessor circuit B accesses the register circuit 139. Thus, the received address information and message information are taken into the microprocessor circuit B.
Several methods for collating the IDs described below are known. The simplest way is to include an ID code register in the ID collating circuit 134. Because this way allows the device to collate the ID code in real-time when it is received, no burden is placed on the microprocessor circuit B. FIG. 35 shows a circuit structure of a prior art serial data receiving apparatus for carrying out this method in the form of a block diagram.
In FIG. 35, a serial data input 131 is input to the synchronizing (or synchronization) circuit 132. When synchronism is established by the synchronizing circuit 132, the data is acquired in succession. The acquired data is corrected as necessary by the error correction circuit 133 and is sent to a buffer register 157 within the ID collating circuit 134. The content of the buffer register 157 is examined and it is determined if it coincides with an ID stored in the ID register circuit 156 or not by the comparison circuit 151. In determining this, the control circuit 154 operates a selector circuit 155 under the timing of the synchronization signal for the serial data input to compare the ID with all IDs within the ID register circuit 156. When the content of the buffer register 157 coincides with one ID among the IDs in the ID register circuit 156, a message is received in succession.
As another method, there is a method of transferring a plurality of ID codes stored in the data RAM in advance sequentially to the ID collating circuit 134 from the microprocessor circuit B when an ID code is received to collate them.
As a still other method, it is conceivable to perform all the collation of the ID codes through the operation of the microprocessor circuit B. In this case, the ID collating circuit 134 becomes unnecessary.
With the recent widespread dissemination of radio communication systems and the diversification of communication services, the number of IDs assigned to portable radio terminals is likely to increase year by year. Thus, terminals which can accommodate flexibly the diversification of the communication systems and communication services will be required along the liberalization of the communication systems and communication services for the future.
As a still other ID controlling portable serial data receiving apparatus used for a pager or the like, one as shown in FIG. 37 in block diagram form has been used in the past. The receiving apparatus comprises a reference clock generating circuit 113 for generating timing signals by receiving an output of an oscillator circuit 111, a synchronizing circuit 132 for synchronizing with data input from a serial data input terminal 131 by receiving the clock output 160, an error correction circuit 133 for detecting and correcting errors in the synchronized and acquired data and an ID collating circuit 134 connected with a bus line of a microprocessor circuit. The clock input to the microprocessor circuit B may be stopped by using a latch 162. The latch 162 is set by a latch data 166 and a latch clock 165 and the setting may be released by a control signal 167. An output of the latch 162 is input to an AND gate 163. A clock output 161 is also input to the AND gate 163 from the reference clock generating circuit 113. An output of the AND gate 163 is input to the microprocessor circuit B as a system clock 164. Accordingly, the system clock 164 may be stopped by writing to the latch 162, putting the microprocessor circuit B into a so-called HALT state.
The microprocessor may be thus put into the halt state at times when it is not necessary by gating the system clock, allowing the system to suppress power consumption.
In FIG. 37, a serial data is input to the synchronizing circuit 132 from outside of the receiving apparatus via a serial data input terminal 131. When synchronism is established by the synchronizing circuit 132, the data is acquired in succession. The acquired data is corrected as necessary by the error correction circuit 133 and it is determined if its ID coincides with a specified ID or not by the ID collating circuit 134. When it is confirmed that the IDs coincide, an interrupt generated by an interrupt request signal 169 is output to the microprocessor circuit B and a message is received in succession. Errors in the received message are corrected similarly to the case of the IDs. The microprocessor circuit B becomes ready to receive the message by receiving an interrupt request and acquires the received message whose errors have been corrected.
With the recent widespread dissemination of radio communication systems and the diversification of communication services, the number of IDs assigned to portable radio terminals is likely to increase year by year. Thus, terminals which can accommodate flexibly the diversification of communication systems and communication services will be required along the liberalization of the communication systems and communication services for the future.
However, when the number of ID codes assigned to the terminal increases, the prior art serial data receiving apparatuses described above require an increase in the number of registers or an increase in the operation clock of the microprocessor circuit B for the collation.
The collation of ID codes normally permits an error of several bits, not requesting a total coincidence. Due to that, the collation by means of software requires a large number of complicated steps. Accordingly, it becomes necessary to increase the clock speed of the microprocessor circuit B in order to collate ID codes while receiving serial data simultaneously. However, there has been a problem in such a case in that the power consumption increases and the receiving sensitivity drops due to noises generated.
Meanwhile, there have been problems in the correlation of ID codes by hardware in that it costs more due to the increase in the size of the hardware and that it lacks flexibility.
Because a syndrome indicates a position of an error bit for one-bit error generated in the received data, the error in the received data may be corrected by a relatively simple circuit. FIG. 11 shows a relationship between error bit positions and syndromes (syndrome vector patterns) when data of 31 bits is received.
In addition, when a two-bit error in received data is to be corrected, it is possible to prepare a pattern which can indicate two error bit positions by taking an exclusive OR of two corresponding syndrome vector patterns per each bit when the error is generated in each bit.
However, there is a problem in that the circuit size of the decoder becomes extremely large because it requires 31xc3x9730xc3x97xc2xd patterns, i.e. 465 types of patterns in the case of 31 bits for example.
Accordingly, it is an object of the invention to provide a data processing unit which allows the correction of a 2-bit error in the received data without increasing the circuit size remarkably.
The prior art circuit has had problems in that it requires N clock pulses for checking every time 1 bit is acquired, and thus requires many circuit operations to detect a word boundary, which increases its power consumption due to signal changes caused by the pulses and it shortens a life of a battery especially when it is used for a portable device. Accordingly, it is an object of the present invention to provide a data processing unit which is adapted to be able to determine and correct errors continuously with less circuit operations, i.e. with less power consumption. It would be impossible to accommodate the increase of a number of necessary IDs if one tried to accommodate a large number of services by using a prior art serial data receiving apparatus. For example, there is a possibility that a contracted ID differs depending on service offerers in receiving services of a plurality of different service offerers by roaming for example. Although it is possible to increase a number of ID registers for example to have many IDs to deal with that, has increases the cost of the equipment because of the increase of the hardware. Due to that, it cannot be increased limitlessly.
But, if all IDs are to be stored in the RAM and are to be collated by a micro-controller, it will not suited for a portable battery-powered device because the power consumption increases.
Further, it has been necessary to stop to receive data once in the past in rewriting IDs when it should be done. Accordingly, there has been a problem in that the receiving has to be stopped once when a service of rewriting an ID in conformity with a code received from a service offerer is to be begun for example. Accordingly, it becomes necessary to start all over again from the establishment of the synchronism in starting again. This increases the probability of received data during the rewriting of the ID.
In the prior art serial data receiving apparatus, the microprocessor circuit B is put into an operative state even in the midst of receiving data when data is stored in the register circuit 139. When the microprocessor circuit B receives an interrupt request from the decoder circuit A, it has to acquire the content of the register circuit 139 before data to be received in succession is written into the register circuit 139 especially in the system not using the DMA. Accordingly, there has been a problem in that if the system clock of the microprocessor circuit B is increased, the power consumption increases and the receiving sensitivity drops due to noises generated.
However, when the number of ID codes assigned to the terminal increases, the prior art serial data receiving apparatuses described above require an increase in the number of registers or an increase in the operation clock speed of the microprocessor circuit B for the collation.
The collation of ID codes normally permits an error of several bits, not requesting a total coincidence. Due to that, the collation by means of software requires a large number of complicated steps. Accordingly, it is necessary to increase the clock speed of the microprocessor circuit B in order to collate ID codes while receiving serial data simultaneously. However, there has been a problem in such a case in that the power consumption increases and the receiving sensitivity drops due to noises generated.
Meanwhile, there have been problems in the correlation or collation of ID codes by hardware in that it costs more due to the increase in the size of the hardware and that it lacks a flexibility.
However, when the number of ID codes assigned to the terminal increases, the prior art serial data receiving apparatuses described above require an increase in the number of registers or an increase in the operation clock speed of the microprocessor circuit B for collation.
The collation of ID codes normally permits an error of several bits, not requesting a total coincidence. Due to that, the collation by means of software requires a large number of complicated steps. Accordingly, it is necessary to increase the clock speed of the microprocessor circuit B in order to collate ID codes while receiving serial data simultaneously. However, there has been a problem in such a case in that the power consumption increases and the receiving sensitivity drops due to noises generated.
Meanwhile, there have been problems in collating ID codes by hardware that it costs more due to the increase of the size in the hardware in and that it lacks a flexibility.
Then, it is conceivable to include a minimum necessary hardware for collating IDs and to compare received ID code with corresponding bits of an assigned ID code per one bit. This method allows a reduced cost, a reduced clock speed and increased flexibly. However, it has had a problem in that along with the increase of bit rate in the received data, a burden on the software increases and the system clock speed is required to be increased.
A first object of the present invention is to provide a receiver including a data processing unit for correcting errors in received data encoded by a cyclic redundancy check code, comprising a data holding section for holding the received data; a checking section for generating and outputting a syndrome in response to the received data and in accordance to the cyclic redundancy check code; a storage section for storing reference syndrome patterns obtained from an exclusive OR of all syndrome patterns when a 1-bit error exists in the received data and a syndrome pattern when an error exists in the most significant bit data of the received data per bit; and a comparison section for outputting an indication of a coincidence when the output data coincides with any one of the reference syndrome patterns in response to an output data from the checking section; the output of the data holding section being corrected when the indication of the coincidence is output from the comparison section.
A second object of the present invention is to provide a receiver including a data processing unit for determining errors in bit serial input data by using a cyclic redundancy check code, comprising a data register capable of holding input data of bits which is equivalent to a sum of a predetermined data length and the cyclic redundancy check code; and a checking circuit for generating a syndrome from the input data in accordance to the cyclic redundancy check code; a level of the input data input to the checking circuit being reversed in accordance to the oldest data in the data register.
A third object of the present invention is to provide a receiver including a serial synchronous receiving apparatus having bit synchronizing means, word synchronizing means, ID storage means, ID collating means, an oscillation circuit, a timing generating circuit, a timer counter and state control means, the state control means for controlling a plurality of receiving modes.
A fourth object of the present invention is to provide a receiver including a serial data receiving apparatus, comprising a decoder circuit having a synchronizing circuit, an ID collating circuit, an error correcting circuit and a control circuit; and a microprocessor circuit having a CPU core circuit, a program ROM and a data RAM connected to the decoder circuit by data buses, address buses and a plurality of signal lines; received data and data accompanying to the received data being stored from the decoder circuit to an area specified in advance in a memory space including the data RAM of the microprocessor circuit regardless of a program executed by the CPU core circuit.
A fifth object of the present invention is to provide a receiver including a serial data receiving apparatus, comprising a decoder circuit having a synchronizing circuit, an ID collating circuit, an error correcting circuit and a control circuit; and a microprocessor circuit having a CPU core circuit, a program ROM and a data RAM connected to the decoder circuit by data buses, address buses and a plurality of signal lines; received data and data accompanying to the received data being stored from the decoder circuit to an area specified in advance in a memory space including the data RAM of the microprocessor circuit by switching the address bus and data bus with a cycle timing of a fetch command of the CPU core circuit.
A sixth object of the present invention is to provide a receiver including a serial data receiving apparatus controlled by a selected paging signal (hereinafter referred to as ID) for acquiring data in synchronism with serial data transmitted through a communication channel characterized in that when it receives the ID code, it collates each bit of the received ID code sequentially by comparing one selected bit within the ID code with a corresponding bit of a plurality of ID codes assigned to the receiving apparatus simultaneously in parallel and by selecting a next bit of the received ID code in succession.
A seventh object of the present invention is to provide a receiver including a serial data receiving apparatus, comprising a microprocessor circuit including a serial data input terminal, a reference clock generating circuit and a central processing unit (hereinafter referred to as CPU); a synchronizing circuit connected with the serial data input terminal and the reference clock generating circuit for synchronizing signals from the serial data input terminal by clocks output from the reference clock generating circuit; a register circuit connected with the synchronizing circuit and the microprocessor circuit and whose setting is made by the microprocessor circuit and whose setting is released by an output signal from the synchronizing circuit; and a gate circuit, connected with the register circuit, the reference clock circuit and the microprocessor circuit, for controlling supply of system clocks output by the reference clock generating circuit to the microprocessor circuit by gating the system clock by an output of the register circuit; a processing program of the microprocessor circuit being executed in synchronism with each bit of the serial data.
In order to solve the aforementioned problems, the present invention is characterized in that the data processing unit for correcting errors in received data encoded by a cyclic redundancy check code comprises the data holding section for holding the received data; the checking section for generating and outputting a syndrome in response to the received data and in accordance to the cyclic redundancy check code; the storage section for storing reference syndrome patterns obtained from an exclusive OR of all syndrome patterns when 1-bit error exists in the received data and a syndrome pattern when an error exists in the most significant bit data of the received data per bit; and the comparison section for outputting an indication of a coincidence when the output data coincides with any one of the reference patterns in response to an output data from the checking section, and that the output of the data holding section is corrected when the indication of the coincidence is output from the comparison section.
In order to solve the aforementioned problems, the apparatus of the present invention utilizes such facts that a syndrome returns to the same value when modulo-two arithmetics to 0 are carried out by a bit number of one word and that the syndrome becomes 1 when an error bit is the most front data. It is characterized in that a data processing unit for determining errors in bit serial input data by using the cyclic redundancy check code comprises the data register for holding input data of bits which is equivalent to a sum of a predetermined data length and the cyclic redundancy check code and a checking circuit for generating a syndrome from the input data in accordance to the cyclic redundancy check code and that a level of the input data input to the checking circuit is reversed in accordance to the oldest data in the data register.
In order to solve such shortcoming of the prior art as described above, the present invention is adapted so as to be able to rewrite IDs in a sufficiently short time while holding the synchronism by setting a PAUSE mode by the state control means, in addition to a timer and receiving mode (RUN mode) of the prior art receiving apparatus.
In order to solve such shortcoming of the prior art as described above, the present invention is adapted so as to store received data and data accompanying to the received data from the decoder circuit to an area specified in advance within a memory space including a data RAM of a microprocessor circuit regardless of a program executed by the CPU core circuit.
In order to solve such shortcoming of the prior art as described above, the present invention realizes a low cost flexible receiving apparatus which can process with low-speed clocks by including a minimum necessary hardware for collating IDs to compare a received ID with a bit of corresponding ID code assigned in advance per bit.
In order to solve such shortcoming of the prior art as described above, the present invention allows processing per bit without any interrupt process by activating the system clock of the microprocessor in synchronism with each bit of received data.
Received data which is data to be checked is held in the data holding section. A syndrome is generated and outputted from the checking section based on the held received data and in accordance to the CRC code. When output data which is the syndrome outputted thus from the checking section coincides with any one of reference syndrome patterns, an indication of coincidence is output from the comparison section and in response to the indication of coincidence, the output of the data holding section is corrected.
Thereby, the influence of bits shifted out in the data register is canceled one by one and the syndrome for the data currently held in the data register may be found without calculating the syndrome each time.
That the syndrome becomes 1 when an error bit comes to the most front even though the modulo-two arithmetic is performed by setting an input of the checking circuit at 0 means that 1 comes in due to the innermost data of the syndrome. Because this data of 1 is caused by the innermost data in the data register, the influence given when the data is acquired first may be canceled by causing an exclusive OR with the innermost data of the syndrome to affect the most front syndrome by the value of the data register.
In the serial data receiving apparatus constructed as described above, both a timer function and a data receiving function are performed at the same time in the normal RUN mode. When no data is received, its power consumption can be remarkably reduced by putting its mode into a STOP mode, while maintaining the timer function. In the PAUSE mode, no IDs are collated, so that IDs can be rewritten while maintaining the timer function and the synchronous state. Due to that, even if ID is changed due to roaming or the like, the same service may be received continuously by rewriting it at each time.
In the serial data receiving apparatus constructed as described above, when the decoder circuit detects data to be received by collating IDs, it receives it and stores in the data RAM. It is stored so that the timing in storing it exerts no effect to the execution of commands of the CPU core circuit and others. Because a storage area in the RAM is specified in advance, the microprocessor circuit can operate without being influenced by the decoder circuit at all if it executes a program while avoiding that area. Further, because the access from the decoder circuit to the data RAM is performed independently, it is not necessary for the microprocessor circuit to operate at high-speed to store data in receiving the data. As a result, a low power consumption and low noise serial data receiving apparatus as a portable equipment may be realized, increasing a life of a battery thereof and enhancing the receiving sensitivity thereof.
In the serial data receiving apparatus constructed as described above, the decoder circuit collates IDs in unit of bit for data successively input after synchronizing the serial data input and correcting errors. The collation of the IDs is carried out by the comparison circuit by comparing the received bit sequentially with a head bit of a plurality of assigned reference ID codes. Because the reference IDs input to the comparison circuit are stored in the RAM of the microprocessor in advance, it may be freely increased/decreased. Further, because the comparison is made by transferring data from the RAM every time when one bit is received, clocks of several to several ten times of bit rate will suffice.
The receiving operation may be facilitated by storing the plurality of reference IDs in the RAM by converting from serial to parallel. It allows the comparison of the received bit with a corresponding bit of the plurality of reference IDs by one time of data transfer from the RAM to the comparison circuit.
In the serial data receiving apparatus constructed as described above, when it is necessary to collate received serial data, a HALT command is executed after finishing the pre-processing, putting into a HALT state at a head of a necessary processing routine. When a synchronism has been established, the HALT state is released every time when one bit is received and necessary processing is carried out automatically. For example, IDs are collated in unit of bit for input data. The collation of the IDs is carried out by the comparison circuit by comparing the received bit sequentially with a head bit of a plurality of assigned reference ID codes. Because the reference IDs input to the comparison circuit are stored in the RAM of the microprocessor in advance, it may be freely increased/decreased. Further, the comparison is made by transferring data from the RAM every time when one bit is received. The HALT state of the microprocessor is released normally by an interrupt. Accordingly, it may be released by generating the interrupt every time when one bit is received. However, a normal microprocessor needs a pre-processing of about 5 machine cycles to enter the interrupt processing. By the way, a number of steps actually needed for the collation of IDs is almost equal or slightly more than this interrupt pre-processing. Due to that, the elimination of the interrupt pre-processing contributes to the reduction of frequency of the system clock and to the decrease of the power consumption.
The receiving operation may be facilitated by storing the plurality of reference IDs in the RAM by converting from serial to parallel. It allows the comparison of the received bit with a corresponding bit of the plurality of reference IDs by one time of data transfer from the RAM to the comparison circuit.